特權(quán)同學(xué)深入淺出玩轉(zhuǎn)FPGA源代碼

ID:391144 · 發(fā)表于 2018-8-29 12:09

特權(quán)同學(xué)深入淺出玩轉(zhuǎn)FPGA課程源代碼

首先，感謝特權(quán)同學(xué)的分享、教導(dǎo)，讓向我這樣的初學(xué)者，能夠有一個(gè)良好的入門平臺(tái)。。言歸正傳，這是我整理出來(lái)的代碼文檔，希望能幫到各位初學(xué)者。

1．分頻器

`timescale 1ns / 1ps
module clkdiv(
clk,rst_n,
clk_div
);
input clk; //50MHz
input rst_n; //低電平復(fù)位信號(hào)
output clk_div; //分頻信號(hào)，連接到蜂鳴器
//---------------------------------------------------
reg[19:0] cnt; //分頻計(jì)數(shù)器
always @ (posedge clk or negedge rst_n) //異步復(fù)位
if(!rst_n) cnt <= 20'd0;
else cnt <= cnt+1'b1; //寄存器cnt 20ms循環(huán)計(jì)數(shù)
//----------------------------------------------------
reg clk_div_r; //clk_div信號(hào)值寄存器
always @ (posedge clk or negedge rst_n)
if(!rst_n) clk_div_r <= 1'b0;
else if(cnt == 20'hfffff) clk_div_r <= ~clk_div_r; //每20ms讓clk_div_r值翻轉(zhuǎn)一次
assign clk_div = clk_div_r;
endmodule

復(fù)制代碼

8．串口發(fā)送接收2
`timescale 1ns / 1ps
module my_uart_tx(clk,rst_n,clk_bps,rx_data,rx_int,rs232_tx,bps_start);
input clk; // 50MHz主時(shí)鐘
input rst_n; //低電平復(fù)位信號(hào)
input clk_bps; // clk_bps的高電平為接收或者發(fā)送數(shù)據(jù)位的中間采樣點(diǎn)
input[7:0] rx_data; //接收數(shù)據(jù)寄存器
input rx_int; //接收數(shù)據(jù)中斷信號(hào),接收到數(shù)據(jù)期間始終為高電平,在此利用它的上升沿來(lái)啟動(dòng)發(fā)送數(shù)據(jù)
output rs232_tx; // RS232發(fā)送數(shù)據(jù)信號(hào)
output bps_start; //接收或者要發(fā)送數(shù)據(jù)，波特率時(shí)鐘啟動(dòng)信號(hào)置位
//---------------------------------------------------------
reg rx_int0,rx_int1,rx_int2; //rx_int信號(hào)寄存器，捕捉下降沿濾波用
wire pos_rx_int; // rx_int下降沿標(biāo)志位
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
rx_int0 <= 1'b0;
rx_int1 <= 1'b0;
rx_int2 <= 1'b0;
end
else begin
rx_int0 <= rx_int;
rx_int1 <= rx_int0;
rx_int2 <= rx_int1;
end
end
assign pos_rx_int = rx_int1 & ~rx_int2; //捕捉到上升沿后，neg_rx_int拉地保持一個(gè)主時(shí)鐘周期
//---------------------------------------------------------
reg[7:0] tx_data; //待發(fā)送數(shù)據(jù)的寄存器
//---------------------------------------------------------
reg bps_start_r;
reg tx_en; //發(fā)送數(shù)據(jù)使能信號(hào)，高有效
reg[3:0] num;
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
bps_start_r <= 1'bz;
tx_en <= 1'b0;
tx_data <= 8'd0;
end
else if(pos_rx_int) begin //接收數(shù)據(jù)完畢，準(zhǔn)備把接收到的數(shù)據(jù)發(fā)出去
bps_start_r <= 1'b1;
tx_data <= rx_data; //把接收到的數(shù)據(jù)存入發(fā)送數(shù)據(jù)寄存器
tx_en <= 1'b1; //進(jìn)入發(fā)送數(shù)據(jù)狀態(tài)中
end
else if(num==4'd11) begin //數(shù)據(jù)發(fā)送完成，復(fù)位
bps_start_r <= 1'b0;
tx_en <= 1'b0;
end
end
assign bps_start = bps_start_r;
//---------------------------------------------------------
reg rs232_tx_r;
always @ (posedge clk or negedge rst_n) begin
if(!rst_n) begin
num <= 4'd0;
rs232_tx_r <= 1'b1;
end
else if(tx_en) begin
if(clk_bps) begin
num <= num+1'b1;
case (num)
4'd0: rs232_tx_r <= 1'b0; //發(fā)送起始位
4'd1: rs232_tx_r <= tx_data[0]; //發(fā)送bit0
4'd2: rs232_tx_r <= tx_data[1]; //發(fā)送bit1
4'd3: rs232_tx_r <= tx_data[2]; //發(fā)送bit2
4'd4: rs232_tx_r <= tx_data[3]; //發(fā)送bit3
4'd5: rs232_tx_r <= tx_data[4]; //發(fā)送bit4
4'd6: rs232_tx_r <= tx_data[5]; //發(fā)送bit5
4'd7: rs232_tx_r <= tx_data[6]; //發(fā)送bit6
4'd8: rs232_tx_r <= tx_data[7]; //發(fā)送bit7
4'd9: rs232_tx_r <= 1'b1; //發(fā)送結(jié)束位
default: rs232_tx_r <= 1'b1;
endcase
end
else if(num==4'd11) num <= 4'd0; //復(fù)位
end
end
assign rs232_tx = rs232_tx_r;
endmodule
`timescale 1ns / 1ps
module ps2_key(clk,rst_n,ps2k_clk,ps2k_data,rs232_tx);
input clk; //50M時(shí)鐘信號(hào)
input rst_n; //復(fù)位信號(hào)
input ps2k_clk; //PS2接口時(shí)鐘信號(hào)
input ps2k_data; //PS2接口數(shù)據(jù)信號(hào)
output rs232_tx; // RS232發(fā)送數(shù)據(jù)信號(hào)
wire[7:0] ps2_byte; // 1byte鍵值
wire ps2_state; //按鍵狀態(tài)標(biāo)志位
wire bps_start; //接收到數(shù)據(jù)后，波特率時(shí)鐘啟動(dòng)信號(hào)置位
wire clk_bps; // clk_bps的高電平為接收或者發(fā)送數(shù)據(jù)位的中間采樣點(diǎn)
ps2scan ps2scan( .clk(clk), //按鍵掃描模塊
.rst_n(rst_n),
.ps2k_clk(ps2k_clk),
.ps2k_data(ps2k_data),
.ps2_byte(ps2_byte),
.ps2_state(ps2_state)
);
speed_select speed_select( .clk(clk),
.rst_n(rst_n),
.bps_start(bps_start),
.clk_bps(clk_bps)
);
my_uart_tx my_uart_tx( .clk(clk),
.rst_n(rst_n),
.clk_bps(clk_bps),
.rx_data(ps2_byte),
.rx_int(ps2_state),
.rs232_tx(rs232_tx),
.bps_start(bps_start)
);
endmodule
`timescale 1ns / 1ps
module ps2scan(clk,rst_n,ps2k_clk,ps2k_data,ps2_byte,ps2_state);
input clk; //50M時(shí)鐘信號(hào)
input rst_n; //復(fù)位信號(hào)
input ps2k_clk; //PS2接口時(shí)鐘信號(hào)
input ps2k_data; //PS2接口數(shù)據(jù)信號(hào)
output[7:0] ps2_byte; // 1byte鍵值，只做簡(jiǎn)單的按鍵掃描
output ps2_state; //鍵盤當(dāng)前狀態(tài)，ps2_state=1表示有鍵被按下
//------------------------------------------
reg ps2k_clk_r0,ps2k_clk_r1,ps2k_clk_r2; //ps2k_clk狀態(tài)寄存器
//wire pos_ps2k_clk; // ps2k_clk上升沿標(biāo)志位
wire neg_ps2k_clk; // ps2k_clk下降沿標(biāo)志位
…………
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ID:267435 · 發(fā)表于 2025-2-27 13:33

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特權(quán)同學(xué)深入淺出玩轉(zhuǎn)FPGA源代碼