3.2 實物圖
file:///C:%5CUsers%5CADMINI%7E1%5CAppData%5CLocal%5CTemp%5Cksohtml%5Cwps151B.tmp.png
FPGA輸出波形:
file:///C:%5CUsers%5CADMINI%7E1%5CAppData%5CLocal%5CTemp%5Cksohtml%5Cwps151C.tmp.png
3.3 實驗程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity love4 is
Port(clk,fankui:in std_logic; --輸入clk，
out1,b0,b1,b2,b3,b4,b5,b6:out std_logic); --輸出
end;
architecture kc2 of love4 is
signal clk1:std_logic;
signal count_4:std_logic_vector(3 downto 0);
signal out_7:std_logic_vector(6 downto 0);
signal cout3:integer range -1 to 40;
begin
b0<=out_7(0);b1<=out_7(1); --將信號賦給輸出
b2<=out_7(2);b3<=out_7(3);
b4<=out_7(4);b5<=out_7(5);
b6<=out_7(6);
process(clk)
variable cnt:integer range 0 to 50000000;
begin
if(clk'event and clk='1') then
cnt:=cnt+1;
if(cnt<25000000) then clk1<='0'; --clk1是250k的方波
elsif(cnt<50000000) then clk1<='1';
else cnt:=0;clk1<='0';
end if;
end if;
end process;
process(a1,b1,clk)
begin
if (clk'event and clk='1') then
if a1='0' then
if sum = 5 then sum <= 0;
else sum <= sum+1;
end if;
elsif b1='0' then --sum-- b1
if sum = 0 then sum <= 5;
else sum <= sum-1;
end if;
end if;
end if;
end process;
process(fankui)
begin
if cout3>19 then cout3<=19;
elsif cout3<0 then cout3<=0;
else
if clk1'event and clk1='1' then
if feed='0' then --反饋信號，0時自減，其他情況自加
cout3<=cout3-1;
else cout3<=cout3+1;
end if;
else null;
end if;
end if;
end process;
process(cout3)
variable cnt,cna:integer range 0 to 50000;
variable i:integer range 0 to 40;
begin
if cnt=50000 then cnt:=0;
else
if clk'event and clk='1' then
if cout3=0 then --分頻出1khz的信號
cnt:=0;
else
cnt:=10000+2000*cout3;
end if;
end if;
end if;
if clk'event and clk='1' then cna:=cna+1;
if cna<cnt then out1<='1'; --通過cna與cnt的比較確定輸出高、低電平
elsif cna<50000 then out1<='0' ;
else cna:=0;out1<='0';
end if;
end if;
end process;
process(cout3)
begin
case cout3 is
when 0=>out_7<="0111111"; --數碼顯示
when 1=>out_7<="0001100";
when 2=>out_7<="1110110";
when 3=>out_7<="1011110";
when 4=>out_7<="1001101";
when 5=>out_7<="1011011";
when 6=>out_7<="1111011";
when 7=>out_7<="0001110";
when 8=>out_7<="1111111";
when 9=>out_7<="1011111";
when others=>out_7<="0111111";
end case;
end process;
end kc2;