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標題: 計數器vhdl代碼 [打印本頁]

作者: 你好11 時間: 2015-7-10 22:06
標題: 計數器vhdl代碼
計數器vhdl代碼。
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ZBF_CHECK IS
PORT(clk,reset:IN STD_LOGIC;
   q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ZBF_CHECK;
ARCHITECTURE struc OF ZBF_CHECK IS
SIGNAL q_temp:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(clk)
BEGIN
IF(clk'EVENT AND clk='1')
THEN
  IF reset='1'
THEN
q_temp<="0000";
  ELSIF q_temp="1001"THEN
q_temp<="0000";
ELSE
q_temp<=q_temp+1;
  END IF;
END IF;
END PROCESS;
q<=q_temp;
END struc;

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