經過實驗 主頻50M的這種DDS最大產生到20K的正弦波就不穩定了不符合題意
1、用自定義IP向導新建IP模板后，在程序目錄的pcores文件夾下回出現IP核文件夾 文件夾中有三個子文件夾：datadevl hdl 首先手動修改data下的.mbp文件，將需要的IO口聲明：
......
PARAMETER C_FAMILY = virtex5, DT = STRING
## Ports
PORT DDS_PWM="", DIR= O,（這句是要添加的）
PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS= SPLB
2、在hdl文件件夾下的VHDL文件夾中的dds_ip.vhd中再次聲明端口
port
(
-- ADD USERPORTS BELOW THIS LINE ------------------
--USER portsadded here
DDS_PWM : out std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
同時在此文件中添加端口對應關系
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
DDS_PWM =>DDS_PWM,
-- MAP USER PORTS ABOVE THIS LINE ------------------
3、在第二部路徑下的user_logic.vhd中編寫邏輯代碼：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
entity user_logic is
generic
(
C_SLV_DWIDTH :integer := 32;
C_NUM_REG :integer := 1
);
port
(
DDS_PWM :out std_logic;
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 toC_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
);
attribute SIGIS : string;
attribute SIGIS ofBus2IP_Clk :signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is"RST";
end entity user_logic;
architecture IMP of user_logic is
constantpwm_0000 : std_logic_vector(0 to 10):="11111010000";
constantpwm_0001 : std_logic_vector(0 to 10):="11111001111";
constantpwm_0002 : std_logic_vector(0 to 10):="11111001110";
。
正弦表，省略2000行
。
constantpwm_1498 : std_logic_vector(0 to 10):="10011100011";
constantpwm_1499 : std_logic_vector(0 to 10):="10011100010";
constantpwm_1500 : std_logic_vector(0 to 10):="10011100010";
signalslv_reg0 : std_logic_vector(0 to 31);
signalslv_reg_write_sel : std_logic_vector(0 to 0);
signalslv_reg_read_sel : std_logic_vector(0 to 0);
signalslv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signalslv_read_ack : std_logic;
signalslv_write_ack : std_logic;
signal cycle : std_logic_vector(0 to31):="00000000000000000000011111010000";
signal hightime : std_logic_vector(0 to31):="00000000000000000000001111101000";
signal tcnt : std_logic_vector(0 to 31);
signal pwm : std_logic;
begin
DDS_PWM<=pwm;
hightime(1 to 31)<=cycle(0 to 30);
process(Bus2IP_Clk,Bus2IP_Reset)
begin
if(Bus2IP_Reset='1')then
tcnt<="00000000000000000000000000000000";
elsif(Bus2IP_Clk'event and Bus2IP_Clk='1')then
if(tcnt=hightime)then
pwm<='0';
tcnt<=tcnt+'1';
elsif(tcnt=cycle)then
pwm<='1';
tcnt<="00000000000000000000000000000000";
else tcnt<=tcnt+'1';
end if;
end if;
end process;
process(Bus2IP_Clk,Bus2IP_Reset)
begin
if(Bus2IP_Reset='1')then
cycle<="00000000000000000000011111010000";
elsif(Bus2IP_Clk'event and Bus2IP_Clk='1')then
case slv_reg0(21 to 31) is
when "00000000000" =>
cycle(21 to 31)<=pwm_0000(0 to 10);
when "00000000001" =>
cycle(21 to 31)<=pwm_0001(0 to 10);
when "00000000010" =>
cycle(21 to 31)<=pwm_0002(0 to 10);
...此出省略4000行 都是和上面一樣的格式
when "10111011011" =>
cycle(21 to 31)<=pwm_1499(0 to 10);
when "10111011100" =>
cycle(21 to 31)<=pwm_1500(0 to 10);
whenothers=>cycle<="00000000000000000000011111010000";
end case;
end if;
end process;
slv_reg_write_sel <= Bus2IP_WrCE(0 to 0);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 0);
slv_write_ack <= Bus2IP_WrCE(0);
slv_read_ack <= Bus2IP_RdCE(0);
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk )is
begin
ifBus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
else
case slv_reg_write_sel is
when "1" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <=Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
SLAVE_REG_READ_PROC : process(slv_reg_read_sel, slv_reg0 ) is
begin
caseslv_reg_read_sel is
when "1" => slv_ip2bus_data <=slv_reg0;
when others => slv_ip2bus_data <=(others => '0');
endcase;
end process SLAVE_REG_READ_PROC;
IP2Bus_Data <= slv_ip2bus_datawhen slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <=slv_write_ack;
IP2Bus_RdAck <=slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
比賽中提到要用數碼管顯示，一般單片機的做法是用軟件去掃描。這樣既浪費時間，又浪費FPGA的資源。這里發一個數碼管硬件掃描的自定義IP核，只要對四個寄存器寫入顯示的數，硬件就自動完成掃描了。
首先，在打data\smg_ip_v2_1_0.mbp文件中添加端口聲明：
...
...
## Ports
PORT SMGs_data_8Bit="", DIR = O, VEC= [0:7]
PORT SMGs_cs_4Bit="", DIR = O, VEC= [0:3]
PORT SPLB_Clk= "", DIR = I, SIGIS = CLK, BUS = SPLB
...
...
第二步，在hdl\vhdl\smg_ip.vhd中添加端口和端口映射：
...
...
port
(
-- ADD USERPORTS BELOW THIS LINE ------------------
--USER portsadded here
SMGs_data_8Bit : out std_logic_vector(0 to 7);
SMGs_cs_4Bit : outstd_logic_vector(0 to3);
-- ADD USER PORTS ABOVE THIS LINE ------------------
...
...
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
SMGs_cs_4Bit => SMGs_cs_4Bit,
SMGs_data_8Bit =>SMGs_data_8Bit,
-- MAP USER PORTS ABOVE THIS LINE ------------------
...
...
最后就是user_logic.vhd里的邏輯代碼：
很多東西都是自動生成的，需要手動編寫的就是前面的自定義端口和邏輯進程
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v2_00_a;
use proc_common_v2_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USERGENERICS BELOW THIS LINE ---------------
--USERgenerics added here
-- ADD USERGENERICS ABOVE THIS LINE ---------------
-- DO NOTEDIT BELOW THIS LINE ---------------------
-- Busprotocol parameters, do not add to or delete
C_SLV_DWIDTH :integer := 32;
C_NUM_REG :integer := 1
-- DO NOTEDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USERPORTS BELOW THIS LINE ------------------
--USER portsadded here
SMGs_data_8Bit : out std_logic_vector(0 to 7);
SMGs_cs_4Bit : out std_logic_vector(0 to 3);
-- ADD USERPORTS ABOVE THIS LINE ------------------
-- DO NOTEDIT BELOW THIS LINE ---------------------
-- Busprotocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 toC_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOTEDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS ofBus2IP_Clk :signal is "CLK";
attribute SIGIS ofBus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, asneeded for user logic
signalsmg_data_out_i : std_logic_vector(0 to 7);
signalsmg_cs_i : std_logic_vector(0 to 3);
signaldiv_cnt : std_logic_vector(0 to 18);
signaldata4 : std_logic_vector(0 to 3);
------------------------------------------
-- Signals for user logic slave model s/waccessible register example
------------------------------------------
signalslv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signalslv_reg_write_sel : std_logic_vector(0 to 0);
signalslv_reg_read_sel : std_logic_vector(0 to 0);
signalslv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signalslv_read_ack : std_logic;
signalslv_write_ack : std_logic;
begin
--USER logic implementation added here
------------------------------------------
-- Example code to read/write user logic slavemodel s/w accessible registers
--
-- Note:
-- The example code presented here is to showyou one way of reading/writing
-- software accessible registers implemented inthe user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCEsignals is configured to correspond
-- to one software accessible register by thetop level template. For example,
-- if you have four 32 bit software accessibleregisters in the user logic,
-- you are basically operating on the followingmemory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE MemoryMapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <=Bus2IP_WrCE(0 to 0);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 0);
slv_write_ack <= Bus2IP_WrCE(0);
slv_read_ack <= Bus2IP_RdCE(0);
SMGs_data_8Bit <= smg_data_out_i;
SMGs_cs_4Bit <= smg_cs_i;
--其實這個文件真正需要自己編的就是以下幾個進程：
process(Bus2IP_Clk,Bus2IP_Reset) --用計數器產生分頻，因為掃描不能太快
begin
if(Bus2IP_Reset='1')then
div_cnt<="0000000000000000000";
elsif(Bus2IP_Clk'event andBus2IP_Clk='1')then
div_cnt<=div_cnt+1;
end if;
end process;
process(Bus2IP_Reset,Bus2IP_Clk,div_cnt(0 to1))--產生掃描信號
begin
if(Bus2IP_Reset='1')then
smg_cs_i<="0000";
elsif(Bus2IP_Clk 'event and Bus2IP_Clk='1')then
casediv_cnt(0 to 1) is
when"00"=> smg_cs_i(0 to3)<="0001";
when"10"=> smg_cs_i(0 to3)<="0010";
when"01"=> smg_cs_i(0 to3)<="0100";
when"11"=> smg_cs_i(0 to3)<="1000";
when others => smg_cs_i(0 to3)<="0000";
endcase;
end if;
end process;
process(smg_cs_i,slv_reg0)--根據不同的掃描信號，數據線上放不同的值
begin
case smg_cs_i(0 to 3)is
when "0001"=>data4(0 to 3)<=slv_reg0(0 to 3);--4位正好表示0-f
when "0010"=>data4(0 to 3)<=slv_reg0(4 to 7);
when "0100"=>data4(0 to 3)<=slv_reg0(8 to 11);
when "1000"=>data4(0 to 3)<=slv_reg0(12 to15);
whenothers => data4<="0000";
end case;
end process;
process(data4)--這個進程相當于解碼
begin
case data4(0 to 3) is
WHEN "0000"=>
smg_data_out_i(0 to 7) <="11111100";
WHEN "0001" =>
smg_data_out_i(0 to 7) <="01100000";
WHEN "0010" =>
smg_data_out_i(0 to 7) <="11011010";
WHEN "0011" =>
smg_data_out_i(0 to 7) <="11110010";
WHEN "0100" =>
smg_data_out_i(0 to 7) <="01100110";
WHEN "0101" =>
smg_data_out_i(0 to 7) <="10110110";
WHEN "0110" =>
smg_data_out_i(0 to 7) <="10111110";
WHEN "0111" =>
smg_data_out_i(0 to 7) <="11100000";
WHEN "1000" =>
smg_data_out_i(0 to 7) <="11111110";
WHEN "1001" =>
smg_data_out_i(0 to 7) <= "11110110";
WHEN "1010" =>
smg_data_out_i(0 to 7) <="11111010";
WHEN "1011" =>
smg_data_out_i(0 to 7) <="00111110";
WHEN "1100" =>
smg_data_out_i(0 to 7) <="10011100";
WHEN "1101" =>
smg_data_out_i(0 to 7) <="01111010";
WHEN "1110" =>
smg_data_out_i(0 to 7) <="10011110";
WHEN "1111" =>
smg_data_out_i(0 to 7) <="10001110";
WHEN OTHERS =>
smg_data_out_i(0 to 7) <= "00000000";
END CASE;
END PROCESS;
--以下是程序自動生成的，分別是與SOC接口寄存器的讀和寫。如果你要對reg讀取的話，要手動將下面的讀取進程刪除，因為VHDL語言中同一個寄存器不能在兩個進程里讀取。
-- implement slave model softwareaccessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk )is
begin
ifBus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
else
case slv_reg_write_sel is
when "1" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <=Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessibleregister(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel,slv_reg0 ) is
begin
caseslv_reg_read_sel is
when "1" => slv_ip2bus_data <=slv_reg0;
when others => slv_ip2bus_data <=(others => '0');
endcase;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <=slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <=slv_write_ack;
IP2Bus_RdAck <=slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
