標題: FPGA之VHDL的74HC161和74HC90court [打印本頁] 作者: heicad 時間: 2014-10-21 15:23 標題: FPGA之VHDL的74HC161和74HC90court 一、74HC161
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity LS74161 is
Port(ENT,ENP,CLK,MR,LD:in std_logic;
D:in std_logic_vector(3 downto 0);
Q:out std_logic_vector(3 downto 0);
Co:out std_logic);
end;
Architecture LS of LS74161 is
signal qq:std_logic_vector(3 downto 0);
begin
process(ENT,ENP,CLK,MR,LD,D)
begin
if ENT='1' and ENP='1' then
if CLK'event and CLK='1' then
if LD='0' then qq<=D;
else qq<=qq+1;
end if;
if qq=15 then Co<='1';
else Co<='0';
end if;
end if;
end if;
end process;
Q<=qq;
end;
二、74HC90
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Entity HC90 is
Port(CLK0,CLK1:in std_logic;
S9,R0:in std_logic_vector(1 downto 0);
Q:out std_logic_vector(2 downto 0);
Q0:out std_logic);
end;
Architecture LS of HC90 is
signal qq:std_logic_vector(2 downto 0);
signal qq0:std_logic;
begin
process(CLK0,CLK1,S9,R0)
begin
if CLK0'event and CLK0='0' then
qq0<=not qq0;
end if;
if CLK1'event and CLK1='0' then
if qq=4 then qq<="000";
else qq<=qq+1;
end if;
end if;
if S9=3 then qq<="100";qq0<='1';
end if;
if R0="11" then qq<="000";qq0<='0';
end if;
end process;
Q<=qq;Q0<=qq0;
end;