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標(biāo)題: VHDL除法器宏模塊及編程調(diào)用 [打印本頁(yè)]

作者: heicad 時(shí)間: 2014-10-17 18:51
標(biāo)題: VHDL除法器宏模塊及編程調(diào)用
1.在要調(diào)用項(xiàng)目的文件夾創(chuàng)建除法器宏模塊
按下圖設(shè)置和添加宏模塊

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.std_logic_arith.all;
Entity dddd is
Port(a:in std_logic_vector(6 downto 0);
   b:in std_logic_vector(3 downto 0);
x:out std_logic_vector(6 downto 0);
y:out std_logic_vector(3 downto 0));
end ;
architecture dd of dddd is
--------定義調(diào)用宏模塊
component chufa is
port(numer:in std_logic_vector(6 downto 0);
   denom:in std_logic_vector(3 downto 0);
quotient:out std_logic_vector(6 downto 0);
   remain:out std_logic_vector(3 downto 0) );
end component;
-----------------結(jié)束定義
begin
U:chufa port map(a,b,x,y);  -----調(diào)用
end;

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