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標題: 關于cyclone V出租車計費系統設計 quartusii 用DE1—soc實驗箱 [打印本頁]

作者: boyplant 時間: 2023-12-13 20:15
標題: 關于cyclone V出租車計費系統設計 quartusii 用DE1—soc實驗箱
需要設計一個出租車計費系統,使用的DE1—soc實驗箱,芯片為cyclone V

我在pwm控制直流電機處加了個計數（標紅部分），下面代碼能實現直流電機轉一圈加1嗎，求求大佬指導怎樣可以讓電機的里程與車費匹配，顯示在數碼管中，數碼管不是一米一米的加。求求了！

基于quartusii的出租車計費器設計試驗箱芯片為cyclone V是DE1—SOC開發板的EDA實驗箱，要求為1.2.1 里程與車費的準確計數：起步價為3元，以后1元每公里，并通過數碼管顯示，前四個數碼管顯示里程，后3個顯示車費。1.2.2 直流電機旋轉模擬車輪的轉動：每轉動一圈認為行走1米，每轉1000圈認為車子前進1公里。1.2.3 綜合：直流電機每轉一圈，計里程的計數器要加1

頂層例化
module w(clk,rst,key_in1,out1,out2,out3,out4,out5,out6,sctrl);
input clk,rst;
input key_in1;
output [6:0]out1,out2,out3,out4,out5,out6;
output sctrl;
wire key_out;
wire [6:0]count;
wire [6:0]PERCENT;
wire [6:0]fee;

xiaodou inst1(clk,rst,key_in1,key_out);
pwm inst2(clk,rst,PERCENT,count,sctrl);
speed inst3(clk,rst,key_out,PERCENT);
jifei inst4(count,rst,fee);
smg inst5(count,out1,out2,out3);
smg inst6(fee,out4,out5,out6);
endmodule

pwm控制直流電機
module pwm
(
      input             clk,
      input             rst,
      input [6:0]PERCENT,
      output reg [6:0]count,
      output       sctrl
);

parameter       CYCLE = 50;
reg pwm_1;
reg [7:0]       cnt_T;

always@(posedge clk or negedge rst)begin
      if (!rst)
      begin
            cnt_T <= 0;
            count<=0;
      end
      else if(cnt_T == CYCLE-1'b1)
      begin
            cnt_T <= 0;
            count<=count+1'b1;
      end
      else
            cnt_T <= cnt_T +1'b1;
end

always@(posedge clk or negedge rst)begin
      if(!rst)
            pwm_1 <= 0;
      else if (cnt_T <= CYCLE * PERCENT /100 -1 )
            pwm_1 <= 1;
      else
            pwm_1 <= 0;
end

assign sctrl=pwm_1;
endmodule
pwm占空比
module speed(clk,rst,key_out,PERCENT);
input clk,rst,key_out;
output reg [6:0]PERCENT;
always@(posedge clk or negedge rst)
begin
if(!rst)
PERCENT<=7'd5;
else if(key_out)
PERCENT<=7'd25;
end

endmodule

消抖
odule xiaodou(clk,rst,key_in1,key_out);
input clk,rst,key_in1;
output key_out;
reg key_value;
reg key_flag;

parameter CNT_20MS=32'd1_000_000;

reg [31:0] cnt_delay;
reg key_reg;

always@(posedge clk or negedge rst)begin
  if (!rst)begin
      cnt_delay<=32'd0;
      key_reg<=1'b1;
      end
  else begin
      key_reg<=key_in1;
      if(key_reg!=key_in1)
         cnt_delay<=CNT_20MS;
      else begin
         if (cnt_delay>32'd0)
            cnt_delay<=cnt_delay-1'b1;
         else
            cnt_delay<=cnt_delay;
         end
  end

end

always @(posedge clk or negedge rst)begin
if(!rst)begin
key_value<=1'b1;
      key_flag<=1'b0;
      end
else  begin
      if (cnt_delay==32'd1)begin
         key_value<=key_in1;
         key_flag<=1'b1;
         end
      else begin
         key_value<=key_value;
         key_flag<=1'b0;
         end
end
end

assign key_out=key_flag && (~key_value);

endmodule

計費
module jifei(count,rst,fee);
input [6:0]count;
input rst;
output reg [6:0]fee;
always@(*)
if(!rst)
fee<=7'd0;
else
fee<=7'd3+(count-7'd1)*7'd1;
endmodule

數碼管顯示
module smg(data,out1,out2,out3);
input [6:0]data;
output reg [6:0]       out1,out2,out3;
always @(*)
begin
      case(data%10)
      7'd0: out1<=7'b1000000;
      7'd1: out1<=7'b1111001;
      7'd2: out1<=7'b0100100;
      7'd3: out1<= 7'b0110000;
      7'd4: out1<= 7'b0011001;
      7'd5: out1<= 7'b0010010;
      7'd6: out1<= 7'b0000010;
      7'd7: out1<= 7'b1111000;
      7'd8: out1<= 7'b0000000;
      7'd9: out1<= 7'b0010000;
      default:out1<=7'b0000000;
      endcase
      end

always@(*)
begin
            case (data%100/10)
                     7'd0 : out2<= 7'b1000000;
                     7'd1 : out2 <= 7'b1111001;
                     7'd2 : out2 <= 7'b0100100;
                     7'd3 : out2 <= 7'b0110000;
                     7'd4 : out2<= 7'b0011001;
                     7'd5 : out2<= 7'b0010010;
                     7'd6 : out2 <= 7'b0000010;
                     7'd7 : out2 <= 7'b1111000;
                     7'd8 : out2 <= 7'b0000000;
                     7'd9 : out2<= 7'b0010000;
                     default : out2 <= 7'b0000000;
            endcase
      end

always @(*)
begin
      case(data/100)
      7'd0: out3<=7'b1000000;
      7'd1: out3<=7'b1111001;
      7'd2: out3<=7'b0100100;
      7'd3: out3<= 7'b0110000;
      7'd4: out3<= 7'b0011001;
      7'd5: out3<= 7'b0010010;
      7'd6: out3<= 7'b0000010;
      7'd7: out3<= 7'b1111000;
      7'd8: out3<= 7'b0000000;
      7'd9: out3<= 7'b0010000;
      default:out3<=7'b0000000;
      endcase
      end

endmodule

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