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標題: STC12單片機硬件SPI實現NRF24L01的發送/接收/中斷接收 [打印本頁]

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作者: michaelchain    時間: 2021-8-29 21:23
標題: STC12單片機硬件SPI實現NRF24L01的發送/接收/中斷接收
今天解決了一個之前困擾很久的1E狀態的問題, 把RX, TX和EXIT+RX的模式都跑通了.

代碼基于HML_FwLib_STC12, 在倉庫的examples里, 鏈接地址
使用的是STC12的硬件SPI的方式, 不是軟件模擬的SPI, 主體代碼如下, 將 CURRENT_MODE 改成不同的值, 會分別啟動到RX, TX和EXTI RX這三種模式, 運行時需要兩塊NRF24L01配合測試.

1. /*****************************************************************************/
   
2. /**
   
3. * \file        spi_nrf24l01_tx.c
   
4. * \date        
   
5. * \brief       Example code of SPI driving NRF24L01 module in TX mode
   
6. * \note        Pin connection:
   
7. *              P1_4(SS, Ignored) => CSN,
   
8. *              P1_5(MOSI)        => MOSI,
   
9. *              P1_6(MISO)        => MISO,
   
10. *              P1_7(SPCLK)       => CLK,
    
11. *              P3_2(INT0)        => IRQ,
    
12. *              P3_7(IO)          => CE,
    
13. *
    
14. * \version     v0.1
    
15. * \ingroup     example
    
16. * \remarks     test-board: Minimum System; test-MCU: STC12C5AF56S2
    
17. ******************************************************************************/
    
18. 
    
19. /*****************************************************************************
    
20. *                             header file                                   *
    
21. *****************************************************************************/
    
22. #include "hml/hml.h"
    
23. #include <stdio.h>
    
24. 
    
25. /**********  SPI(nRF24L01) commands  ***********/
    
26. //
    
27. #define NRF24_CMD_REGISTER_R     0x00 // Register read
    
28. #define NRF24_CMD_REGISTER_W     0x20 // Register write
    
29. #define NRF24_CMD_ACTIVATE       0x50 // (De)Activates R_RX_PL_WID, W_ACK_PAYLOAD, W_TX_PAYLOAD_NOACK features
    
30. #define NRF24_CMD_RX_PLOAD_WID_R 0x60 // Read RX-payload width for the top R_RX_PAYLOAD in the RX FIFO.
    
31. #define NRF24_CMD_RX_PLOAD_R     0x61 // Read RX payload
    
32. #define NRF24_CMD_TX_PLOAD_W     0xA0 // Write TX payload
    
33. #define NRF24_CMD_ACK_PAYLOAD_W  0xA8 // Write ACK payload
    
34. #define NRF24_CMD_TX_PAYLOAD_NOACK_W 0xB0 //Write TX payload and disable AUTOACK
    
35. #define NRF24_CMD_FLUSH_TX       0xE1 // Flush TX FIFO
    
36. #define NRF24_CMD_FLUSH_RX       0xE2 // Flush RX FIFO
    
37. #define NRF24_CMD_REUSE_TX_PL    0xE3 // Reuse TX payload
    
38. #define NRF24_CMD_LOCK_UNLOCK    0x50 // Lock/unlock exclusive features
    
39. #define NRF24_CMD_NOP            0xFF // No operation (used for reading status register)
    
40. 
    
41. 
    
42. // SPI(nRF24L01) register address definitions
    
43. #define NRF24_REG_CONFIG         0x00 // Configuration register
    
44. #define NRF24_REG_EN_AA          0x01 // Enable "Auto acknowledgment"
    
45. #define NRF24_REG_EN_RXADDR      0x02 // Enable RX addresses
    
46. #define NRF24_REG_SETUP_AW       0x03 // Setup of address widths
    
47. #define NRF24_REG_SETUP_RETR     0x04 // Setup of automatic re-transmit
    
48. #define NRF24_REG_RF_CH          0x05 // RF channel
    
49. #define NRF24_REG_RF_SETUP       0x06 // RF setup
    
50. #define NRF24_REG_STATUS         0x07 // Status register
    
51. #define NRF24_REG_OBSERVE_TX     0x08 // Transmit observe register
    
52. #define NRF24_REG_RPD            0x09 // Received power detector
    
53. #define NRF24_REG_RX_ADDR_P0     0x0A // Receive address data pipe 0
    
54. #define NRF24_REG_RX_ADDR_P1     0x0B // Receive address data pipe 1
    
55. #define NRF24_REG_RX_ADDR_P2     0x0C // Receive address data pipe 2
    
56. #define NRF24_REG_RX_ADDR_P3     0x0D // Receive address data pipe 3
    
57. #define NRF24_REG_RX_ADDR_P4     0x0E // Receive address data pipe 4
    
58. #define NRF24_REG_RX_ADDR_P5     0x0F // Receive address data pipe 5
    
59. #define NRF24_REG_TX_ADDR        0x10 // Transmit address
    
60. #define NRF24_REG_RX_PW_P0       0x11 // Number of bytes in RX payload in data pipe 0
    
61. #define NRF24_REG_RX_PW_P1       0x12 // Number of bytes in RX payload in data pipe 1
    
62. #define NRF24_REG_RX_PW_P2       0x13 // Number of bytes in RX payload in data pipe 2
    
63. #define NRF24_REG_RX_PW_P3       0x14 // Number of bytes in RX payload in data pipe 3
    
64. #define NRF24_REG_RX_PW_P4       0x15 // Number of bytes in RX payload in data pipe 4
    
65. #define NRF24_REG_RX_PW_P5       0x16 // Number of bytes in RX payload in data pipe 5
    
66. #define NRF24_REG_FIFO_STATUS    0x17 // FIFO status register
    
67. #define NRF24_REG_DYNPD          0x1C // Enable dynamic payload length
    
68. #define NRF24_REG_FEATURE        0x1D // Feature register
    
69. 
    
70. // Register bits definitions
    
71. #define NRF24_CONFIG_PRIM_RX     0x01 // PRIM_RX bit in CONFIG register
    
72. #define NRF24_CONFIG_PWR_UP      0x02 // PWR_UP bit in CONFIG register
    
73. #define NRF24_FEATURE_EN_DYN_ACK 0x01 // EN_DYN_ACK bit in FEATURE register
    
74. #define NRF24_FEATURE_EN_ACK_PAY 0x02 // EN_ACK_PAY bit in FEATURE register
    
75. #define NRF24_FEATURE_EN_DPL     0x04 // EN_DPL bit in FEATURE register
    
76. #define NRF24_FLAG_RX_DREADY     0x40 // RX_DR bit (data ready RX FIFO interrupt)
    
77. #define NRF24_FLAG_TX_DSENT      0x20 // TX_DS bit (data sent TX FIFO interrupt)
    
78. #define NRF24_FLAG_MAX_RT        0x10 // MAX_RT bit (maximum number of TX re-transmits interrupt)
    
79. 
    
80. // Register masks definitions
    
81. #define NRF24_MASK_REG_MAP       0x1F // Mask bits[4:0] for CMD_RREG and CMD_WREG commands
    
82. #define NRF24_MASK_CRC           0x0C // Mask for CRC bits [3:2] in CONFIG register
    
83. #define NRF24_MASK_STATUS_IRQ    0x70 // Mask for all IRQ bits in STATUS register
    
84. #define NRF24_MASK_RF_PWR        0x06 // Mask RF_PWR[2:1] bits in RF_SETUP register
    
85. #define NRF24_MASK_RX_P_NO       0x0E // Mask RX_P_NO[3:1] bits in STATUS register
    
86. #define NRF24_MASK_DATARATE      0x28 // Mask RD_DR_[5,3] bits in RF_SETUP register
    
87. #define NRF24_MASK_EN_RX         0x3F // Mask ERX_P[5:0] bits in EN_RXADDR register
    
88. #define NRF24_MASK_RX_PW         0x3F // Mask [5:0] bits in RX_PW_Px register
    
89. #define NRF24_MASK_RETR_ARD      0xF0 // Mask for ARD[7:4] bits in SETUP_RETR register
    
90. #define NRF24_MASK_RETR_ARC      0x0F // Mask for ARC[3:0] bits in SETUP_RETR register
    
91. #define NRF24_MASK_RXFIFO        0x03 // Mask for RX FIFO status bits [1:0] in FIFO_STATUS register
    
92. #define NRF24_MASK_TXFIFO        0x30 // Mask for TX FIFO status bits [5:4] in FIFO_STATUS register
    
93. #define NRF24_MASK_PLOS_CNT      0xF0 // Mask for PLOS_CNT[7:4] bits in OBSERVE_TX register
    
94. #define NRF24_MASK_ARC_CNT       0x0F // Mask for ARC_CNT[3:0] bits in OBSERVE_TX register
    
95. 
    
96. #define NRF24_ADDR_WIDTH         5    // RX/TX address width
    
97. #define NRF24_PLOAD_WIDTH        32   // Payload width
    
98. #define NRF24_TEST_ADDR          "nRF24"
    
99. 
    
100. typedef enum
     
101. {
     
102.     NRF24_MODE_RX = 0x00,
     
103.     NRF24_MODE_TX = 0x01,
     
104.     NRF24_MODE_IT = 0x02
     
105. } NRF24_MODE;
     
106. 
     
107. const uint8_t TX_ADDRESS[NRF24_ADDR_WIDTH] = {0x32,0x4E,0x6F,0x64,0x65};
     
108. const uint8_t RX_ADDRESS[NRF24_ADDR_WIDTH] = {0x32,0x4E,0x6F,0x64,0x22};
     
109. const NRF24_MODE CURRENT_MODE = NRF24_MODE_IT;
     
110. uint8_t rx_buf[NRF24_PLOAD_WIDTH];
     
111. 
     
112. #define NRF_CSN  P1_4
     
113. #define NRF_MOSI P1_5
     
114. #define NRF_MISO P1_6
     
115. #define NRF_SCK  P1_7
     
116. #define NRF_IRQ  P3_2
     
117. #define NRF_CE   P3_7
     
118. 
     
119. 
     
120. uint8_t NRF24L01_Write_Reg(uint8_t reg,uint8_t value)
     
121. {
     
122.         uint8_t status;
     
123. 
     
124.         NRF_CSN = 0;
     
125.           status = SPI_RW(reg);
     
126.         SPI_RW(value);
     
127.         NRF_CSN = 1;
     
128.         return status;
     
129. }
     
130. 
     
131. uint8_t NRF24L01_Read_Reg(uint8_t reg)
     
132. {
     
133.     uint8_t value;
     
134.     NRF_CSN = 0;
     
135.     SPI_RW(reg);
     
136.     value = SPI_RW(NRF24_CMD_NOP);
     
137.     NRF_CSN = 1;
     
138.     return value;
     
139. }
     
140. 
     
141. uint8_t NRF24L01_Read_To_Buf(uint8_t reg, uint8_t *pBuf, uint8_t len)
     
142. {
     
143.     uint8_t status, u8_ctr;
     
144.     NRF_CSN = 0;
     
145.     status = SPI_RW(reg);
     
146.     for (u8_ctr = 0; u8_ctr < len; u8_ctr++)
     
147.         pBuf[u8_ctr] = SPI_RW(NRF24_CMD_NOP);
     
148.     NRF_CSN = 1;
     
149.     return status;
     
150. }
     
151. 
     
152. uint8_t NRF24L01_Write_From_Buf(uint8_t reg, const uint8_t *pBuf, uint8_t len)
     
153. {
     
154.     uint8_t status, u8_ctr;
     
155.     NRF_CSN = 0;
     
156.     status = SPI_RW(reg);
     
157.     for (u8_ctr = 0; u8_ctr < len; u8_ctr++)
     
158.         SPI_RW(*pBuf++);
     
159.     NRF_CSN = 1;
     
160.     return status;
     
161. }
     
162. 
     
163. /**
     
164. * Flush the RX FIFO
     
165. */
     
166. void NRF24L01_FlushRX(void)
     
167. {
     
168.         NRF24L01_Write_Reg(NRF24_CMD_FLUSH_RX, NRF24_CMD_NOP);
     
169. }
     
170. 
     
171. /**
     
172. * Flush the TX FIFO
     
173. */
     
174. void NRF24L01_FlushTX(void)
     
175. {
     
176.         NRF24L01_Write_Reg(NRF24_CMD_FLUSH_TX, NRF24_CMD_NOP);
     
177. }
     
178. 
     
179. /**
     
180. * Clear IRQ bit of the STATUS register
     
181. *   reg - NRF24_FLAG_RX_DREADY
     
182. *         NRF24_FLAG_TX_DSENT
     
183. *         NRF24_FLAG_MAX_RT
     
184. */
     
185. void NRF24L01_ClearIRQFlag(uint8_t reg)
     
186. {
     
187.   NRF24L01_Write_Reg(NRF24_CMD_REGISTER_W + NRF24_REG_STATUS, reg);
     
188. }
     
189. 
     
190. /**
     
191. * Clear RX_DR, TX_DS and MAX_RT bits of the STATUS register
     
192. */
     
193. void NRF24L01_ClearIRQFlags(void)
     
194. {
     
195.         uint8_t reg;
     
196.         reg  = NRF24L01_Read_Reg(NRF24_REG_STATUS);
     
197.         reg |= NRF24_MASK_STATUS_IRQ;
     
198.         NRF24L01_Write_Reg(NRF24_REG_STATUS, reg);
     
199. }
     
200. 
     
201. uint8_t NRF24L01_RxPacket(uint8_t *rxbuf)
     
202. {
     
203.     while(NRF_IRQ);
     
204. 
     
205.     uint8_t state = NRF24L01_Read_Reg(NRF24_REG_STATUS);
     
206.     printf_tiny("Interrupted, state: %x\r\n", state);
     
207.     NRF24L01_Write_Reg(NRF24_CMD_REGISTER_W + NRF24_REG_STATUS, state);
     
208.     if (state & NRF24_FLAG_RX_DREADY)
     
209.     {
     
210.         NRF24L01_Read_To_Buf(NRF24_CMD_RX_PLOAD_R, rxbuf, NRF24_PLOAD_WIDTH);
     
211.         NRF24L01_FlushRX();
     
212.     }
     
213.     return state;
     
214. }
     
215. 
     
216. uint8_t NRF24L01_TxPacket(uint8_t *txbuf)
     
217. {
     
218.     uint8_t state;
     
219.     NRF_CE = 0;
     
220.     NRF24L01_Write_From_Buf(NRF24_CMD_TX_PLOAD_W, txbuf, NRF24_PLOAD_WIDTH);
     
221.     NRF_CE = 1;
     
222.     while (NRF_IRQ == 1);
     
223.     state = NRF24L01_Read_Reg(NRF24_REG_STATUS);
     
224.     NRF24L01_Write_Reg(NRF24_CMD_REGISTER_W + NRF24_REG_STATUS, state);
     
225.     if (state & NRF24_FLAG_MAX_RT)
     
226.     {
     
227.         NRF24L01_FlushTX();
     
228.         NRF24L01_ClearIRQFlag(NRF24_FLAG_MAX_RT);
     
229.     }
     
230.     if (state & NRF24_FLAG_TX_DSENT)
     
231.     {
     
232.         NRF24L01_ClearIRQFlag(NRF24_FLAG_TX_DSENT);
     
233.     }
     
234.     return state;
     
235. }
     
236. 
     
237. uint8_t NRF24L01_Check(void)
     
238. {
     
239.         uint8_t i;
     
240.         uint8_t *ptr = (uint8_t *)NRF24_TEST_ADDR;
     
241.         NRF24L01_Write_From_Buf(NRF24_CMD_REGISTER_W | NRF24_REG_TX_ADDR, ptr, NRF24_ADDR_WIDTH);
     
242.         NRF24L01_Read_To_Buf(NRF24_CMD_REGISTER_R | NRF24_REG_TX_ADDR, rx_buf, NRF24_ADDR_WIDTH);
     
243.         for (i = 0; i < NRF24_ADDR_WIDTH; i++) {
     
244.                 if (rx_buf[i] != *ptr++) return 1;
     
245.         }
     
246.         return 0;
     
247. }
     
248. 
     
249. void NRF24L01_init(NRF24_MODE mode)
     
250. {
     
251.     NRF_CE = 0;
     
252.     NRF24L01_Write_Reg(NRF24_CMD_REGISTER_W + NRF24_REG_RX_PW_P0, NRF24_PLOAD_WIDTH);
     
253.     NRF24L01_Write_From_Buf(NRF24_CMD_REGISTER_W + NRF24_REG_TX_ADDR, (uint8_t *)TX_ADDRESS, NRF24_ADDR_WIDTH);
     
254.     NRF24L01_Write_Reg(NRF24_CMD_REGISTER_W + NRF24_REG_EN_AA, 0x3f);
     
255.     NRF24L01_Write_Reg(NRF24_CMD_REGISTER_W + NRF24_REG_EN_RXADDR, 0x3f);
     
256.     NRF24L01_Write_Reg(NRF24_CMD_REGISTER_W + NRF24_REG_SETUP_RETR, 0x0a);
     
257.     NRF24L01_Write_Reg(NRF24_CMD_REGISTER_W + NRF24_REG_RF_CH, 40);
     
258.     NRF24L01_Write_Reg(NRF24_CMD_REGISTER_W + NRF24_REG_RF_SETUP, 0x07);
     
259.     switch (mode)
     
260.     {
     
261.         case NRF24_MODE_RX:
     
262.         case NRF24_MODE_IT:
     
263.             NRF24L01_Write_From_Buf(NRF24_CMD_REGISTER_W + NRF24_REG_RX_ADDR_P0, (uint8_t *)RX_ADDRESS, NRF24_ADDR_WIDTH);
     
264.             NRF24L01_Write_Reg(NRF24_CMD_REGISTER_W + NRF24_REG_CONFIG, 0x0F);
     
265.             break;
     
266.         case NRF24_MODE_TX:
     
267.         default:
     
268.             NRF24L01_Write_From_Buf(NRF24_CMD_REGISTER_W + NRF24_REG_RX_ADDR_P0, (uint8_t *)TX_ADDRESS, NRF24_ADDR_WIDTH);
     
269.             NRF24L01_Write_Reg(NRF24_CMD_REGISTER_W + NRF24_REG_CONFIG, 0x0E);
     
270.             break;
     
271.     }
     
272.     NRF_CE = 1;
     
273. }
     
274. 
     
275. void NRF24L01_printBuf(void)
     
276. {
     
277.     for (uint8_t i = 0; i < NRF24_PLOAD_WIDTH; i++)
     
278.     {
     
279.         printf_tiny("%x ", rx_buf[i]);
     
280.     }
     
281.     printf_tiny("\r\n");
     
282. }
     
283. 
     
284. void NRF24L01_irqHandler(void) __interrupt IE0_VECTOR
     
285. {
     
286.     uint8_t state = NRF24L01_Read_Reg(NRF24_REG_STATUS);
     
287.     printf_tiny("Interrupted, state: %x\r\n", state);
     
288.     NRF24L01_Write_Reg(NRF24_CMD_REGISTER_W + NRF24_REG_STATUS, state);
     
289.     if (state & NRF24_FLAG_RX_DREADY)
     
290.     {
     
291.         NRF24L01_Read_To_Buf(NRF24_CMD_RX_PLOAD_R, rx_buf, NRF24_PLOAD_WIDTH);
     
292.         NRF24L01_FlushRX();
     
293.         NRF24L01_printBuf();
     
294.     }
     
295. }
     
296. 
     
297. void EXTI_init(void)
     
298. {
     
299.     EXTI_configTypeDef ec;
     
300. 
     
301.     ec.mode     = EXTI_mode_lowLevel;
     
302.     ec.priority = IntPriority_High;
     
303.     EXTI_config(PERIPH_EXTI_0, &ec);
     
304.     EXTI_cmd(PERIPH_EXTI_0, ENABLE);
     
305.     UTIL_setInterrupts(ENABLE);
     
306. }
     
307. 
     
308. void SPI_init(void)
     
309. {
     
310.     SPI_configTypeDef sc;
     
311.     sc.baudRatePrescaler = SPI_BaudRatePrescaler_4;
     
312.     sc.cpha = SPI_CPHA_1Edge;
     
313.     sc.cpol = SPI_CPOL_low;
     
314.     sc.firstBit = SPI_FirstBit_MSB;
     
315.     sc.pinmap = SPI_pinmap_P1;
     
316.     sc.nss = SPI_NSS_Soft;
     
317.     sc.mode = SPI_Mode_Master;
     
318.     SPI_config(&sc);
     
319.     SPI_cmd(ENABLE);
     
320. }
     
321. 
     
322. void main(void)
     
323. {
     
324.     UTIL_enablePrintf();
     
325.     SPI_init();
     
326. 
     
327.     while (NRF24L01_Check())
     
328.     {
     
329.         printf_tiny("Check failed, waiting retry\r\n");
     
330.         sleep(500);
     
331.     }
     
332. 
     
333.     NRF24L01_init(CURRENT_MODE);
     
334. 
     
335.     if (CURRENT_MODE == NRF24_MODE_RX)
     
336.     {
     
337.         while (true)
     
338.         {
     
339.             uint8_t sta = NRF24L01_RxPacket(rx_buf);
     
340.             printf_tiny("RX stat: %x\r\n", sta);
     
341.             NRF24L01_printBuf();
     
342.         }
     
343.     }
     
344.     else if (CURRENT_MODE == NRF24_MODE_IT)
     
345.     {
     
346.         EXTI_init();
     
347.         while(true);
     
348.     }
     
349.     else
     
350.     {
     
351.         uint8_t tmp[] = {
     
352.             0x1F, 0x80, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18,
     
353.             0x21, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x28,
     
354.             0x31, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x38,
     
355.             0x41, 0x12, 0x13, 0x14, 0x15, 0x16, 0x37, 0x48};
     
356.         while (true)
     
357.         {
     
358.             uint8_t sta = NRF24L01_TxPacket(tmp);
     
359.             tmp[1] = sta;
     
360.             printf_tiny("TX stat: %x\r\n", sta);
     
361.             sleep(500);
     
362.         }
     
363.     }
     
364. }
     

復制代碼

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