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標題: 模8計數(shù)器verilog程序 [打印本頁]

作者: LeeYX 時間: 2019-7-2 12:27
標題: 模8計數(shù)器verilog程序
模8計數(shù)器的功能模塊如下：
module counter_8(clock,clear,q);
input clock,clear;
output[2:0] q;
reg[2:0] q;

always @(posedge clock or negedge clear)
begin
if(!clear)
q<=0;
else
q <= q +1;
end
endmodule

測試激勵如下：
module test_counter8;

reg clk,clr;
wire[2:0] q;
counter_8 counter(.clock(clk),.clear(clr),.q(q));
initial
clk = 0;
always
#100 clk = ~clk;
initial
begin
clr = 0;
#50 clr = 1;
#200 clr = 0;
#50 clr = 1;
end
initial
$monitor($time,"clear= %b,clock= %b,q= %b",clr,clk,q);
endmodule

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