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標題: Verilog數碼管問題求助 [打印本頁]

作者: 宮梓萱 時間: 2017-12-25 16:53
標題: Verilog數碼管問題求助
這是代碼：問題是：//data是要在數碼管上顯示的數，但他只能顯示十六進制下的數，因為1995的十六進制是07cb，因此在四位一體共陰數碼管上就只顯示07CB，我怎么讓他在十進制下顯示，比如十進制下的1995，就讓他顯示1995而不是07CB。

module smg(clk,rst,duan,wei);
input clk,rst;
reg [15:0] data=16'd1995;  //待顯示的數據

output reg[7:0]  duan;
output reg[3:0]  wei;

reg[25:0] cnt;
reg clk_1K;
reg[3:0] buff;
reg[1:0] index;

always @(posedge clk or negedge rst)
      if(!rst) cnt<=26'd0;
   else if(cnt==26'd25000) cnt<=26'd0;
   else cnt<=cnt+1'b1;

always @(posedge clk or negedge rst) //產生1KHz時鐘
      if(!rst) clk_1K<=1'b0;
      else if(cnt==26'd25000) clk_1K<=~clk_1K;

always @(posedge clk_1K or negedge rst)
      if(!rst) index<=2'd0;
   else index<=index+1'b1;

always @(posedge clk or negedge rst) begin
      case(index)
      3:wei<=4'b0111;
2:wei<=4'b1011;
1:wei<=4'b1101;
0:wei<=4'b1110;
   endcase
end

always @(posedge clk or negedge rst)
      if(!rst)  buff<=4'd0;
   else begin
         case(wei)
      4'd7:buff<=data[3:0];
      4'd11:buff<=data[7:4];
   4'd13:buff<=data[11:8];
   4'd14:buff<=data[15:12];
   endcase
   end

always @(posedge clk or negedge rst)
      if(!rst) duan<=8'b0000_0000;
   else begin
         case(buff)
   4'h0: duan <= 8'h3f; //0
         4'h1: duan <= 8'h06; //1
         4'h2: duan <= 8'h5b; //2
         4'h3: duan <= 8'h4f; //3
         4'h4: duan <= 8'h66; //4
         4'h5: duan <= 8'h6d; //5
         4'h6: duan <= 8'h7d; //6
         4'h7: duan <= 8'h07; //7
         4'h8: duan <= 8'h7f; //8
         4'h9: duan <= 8'h6f; //9
         4'ha: duan <= 8'h77; //a
         4'hb: duan <= 8'h7c; //b
         4'hc: duan <= 8'h39; //c
         4'hd: duan <= 8'h5e; //d
         4'he: duan <= 8'h79; //e
         4'hf: duan <= 8'h71; //f
         endcase
      end

endmodule

作者: 出來逛逛 時間: 2017-12-26 11:05
把輸入數據處理一下，變成8421BCD碼，按位顯示就行了

作者: 小六 時間: 2017-12-27 09:19
verilog左移加三法，二進制轉bcd碼

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